1. Field of the Invention
This invention relates to a semiconductor chip that has a through-hole penetrating in its thickness direction, a method for manufacturing the semiconductor chip, a semiconductor device that has a semiconductor chip having a through-hole penetrating in its thickness direction, and a method for manufacturing the semiconductor device.
2. Description of Related Art
A multichip module (MCM) is known as a semiconductor device having a plurality of semiconductor chips. In the multichip module, an attempt has been made to reduce the mounting area of a semiconductor device by stacking a plurality of semiconductor chips together on a wiring substrate in the semiconductor device. In some of the thus structured semiconductor devices, a penetration electrode is provided in a through-hole penetrating through semiconductor chips in the thickness direction, and a longitudinal electrical connection is achieved by this penetration electrode.
FIG. 13A to FIG. 13H are diagrammatic sectional views for explaining a conventional method for manufacturing a semiconductor chip having a penetration electrode. This method is disclosed by Japanese translation of International Application (Kohyo) No. 2000-510288.
A hard mask 103 having an opening 103a in which a region beside a functional device 101 is exposed is formed on a surface of a semiconductor wafer (hereinafter, referred to simply as “wafer”) W on one surface (hereinafter, referred to as “front surface”) of which the functional device 101 is provided.
Thereafter, a front-surface-side concave portion 102 that has a depth smaller than the thickness of the wafer W is formed in the region beside the functional device 101 by carrying out reactive ion etching (RIE) where the hard mask 103 is used as a mask, whereafter a contact hole 103b in which a predetermined part of the functional device 101 is exposed is formed in the hard mask 103.
Thereafter, an insulating film 104 made of silicon oxide is formed on the exposed surface in the opening 103a and the exposed surface in the front-surface-side concave portion 102. FIG. 13A shows this state.
Thereafter, an electroconductive diffusion-preventing film 105 is formed on the whole of the front surface of the wafer W that has undergone the foregoing steps (see FIG. 13B), and a seed layer (not shown) is formed on the diffusion preventing film 105. The inside of the opening 103a, the inside of the contact hole 103b, and the inside of the front-surface-side concave portion 102 are then filled with a metal film 106 made of copper by carrying out electrolytic plating where the seed layer is used a seed. Accordingly, the metal film 106 is electrically connected to the functional device 101 through the contact hole 103b. FIG. 13C shows this state.
Thereafter, a part of the metal film 106 and a part of the diffusion preventing film 105 are removed, except for the inside of the front-surface-side concave portion 102, the opening 103a, and the contact hole 103b and except for a predetermined region having a pattern that makes a connection between the inside of the opening 103a and the inside of the contact hole 103b. FIG. 13D shows this state.
Thereafter, a UBM layer 107 and a bump 108 are formed on the metal film 106 outside the front-surface-side concave portion 102, the opening 103a, and the contact hole 103b. The UBM layer 107 lies between the metal film 106 and the bump 108. FIG. 13E shows this state.
Thereafter, the front surface of the wafer W is stuck onto a supporter (not shown), and the rear surface Wr of the wafer W is mechanically ground, whereby the wafer W is thinned. As a result, the front-surface-side concave portion 102 becomes a through-hole 112, and the metal film 106 is exposed to the rear surface Wr of the wafer W. The metal film 106 in the front-side concave portion 102 and in the opening 103a becomes a penetration electrode 109. The remainder of the metal film 106 integral with the penetration electrode 109 functions as a wiring member 110 through which the penetration electrode 109 and the functional device 101 are electrically connected to each other. FIG. 13F shows this state.
A grinding damage layer, which has grinding marks or damage received when ground, exists on the rear surface Wr of the wafer W. To remove the grinding damage layer, the rear surface Wr of the wafer W is subjected to dry etching by approximately 5 μm. At this time, the penetration electrode 109, the diffusion preventing film 105, and the insulating film 104 are hardly etched, and jut from the rear surface Wr of the wafer W. FIG. 13G shows this state.
Thereafter, a rear-surface-side insulating film 111 made of silicon oxide is formed on the whole of the rear surface Wr of the wafer W, and then a part of the insulating film 111, with which the penetration electrode 109, the diffusion preventing film 105, and the insulating film 104 are covered, is ground, is removed, and is exposed (see FIG. 13H). Thereafter, the wafer W is cut into semiconductor chips, each having the penetration electrode 109.
Semiconductor chips obtained according to the manufacturing method described above are stacked together in the longitudinal direction, and the bump 108 of each of the adjoining semiconductor chips is joined to the penetration electrode 109 of the adjoining semiconductor chip, the penetration electrode 109 being exposed at the rear surface Wr of the wafer W, whereby the semiconductor chips can be electrically connected together. Therefore, the wiring length can be shortened. In the thus structured semiconductor device, the mounting area with respect to, for example, the wiring substrate is small.
However, according to the conventional method for manufacturing a semiconductor chip that has a penetration electrode 109, not only the wafer W but also the metal film 106 (the penetration electrode 109) is ground when the rear surface Wr of the wafer W is ground (see FIG. 13F). Therefore, the copper forming the metal film 106 reaches to a deep part of the wafer W from the rear surface Wr of the wafer W because of diffusion, and remains in the wafer W even if a grinding damage layer is removed (see FIG. 13G). Thus, the wafer W is contaminated, and the properties of the semiconductor chip are deteriorated.